The computing speed and data transfer rates of computer systems continues to increase. In order to provide data at a fast enough rate to such systems, the speed at which memory storage devices operate has also increased. Common types of memory storage devices include semiconductor random access memories (RAM), such as dynamic RAMs (DRAMs) and static RAMs (SRAMs), and read only memories (ROMs), such as electrically erasable programmable ROMs (EEPROMs). RAMs and ROMs having rapid access speeds are thus desirable for high speed systems.
In a typical RAM or ROM, the memory device includes a number of memory cells for storing data. Data within the memory cell can be accessed by a read or write operation (in the case of a RAM), or a read or program operation (in the case of a ROM). In most RAMs and ROMs, a read operation results in memory cells being coupled to bit lines to generate data signals on the bit lines. Because memory cells are usually manufactured as small as possible, the data signals on the bit lines are correspondingly small (i.e., a small current signal or small voltage differential). In order to translate the such small data signals into output data signals, the memory cell data signals must first be amplified. Such amplification operations are often referred to as "sensing" and are performed by amplifying circuits referred to as sense amplifiers. Because memory cell data signals must first be sensed before they are output, the speed at which data can be sensed plays an important role in the overall access speed of a semiconductor memory device.
In order to sense data, sense amplifiers typically charge or discharge a bit line (or bit line pair) according to the memory cell data value. In order to charge the relatively large capacitive load presented by a bit line, a sense amplifier will draw current from the power supply. The maximum current drawn by the sense amplifiers during a sense operation is referred to as a peak current. While high peak currents are undesirable, due to their resulting power consumption and noise generation, the ability of RAM or ROM to provide a high peak current can lead to faster sensing times.
In addition to amplifying memory cell data signals to generate output signals, sensing operations also play an important role in DRAMs. DRAM memory cells typically store data values by charging a storage charge capacitor situated within each memory cell. Because stored can leak out over time, the charge within such a capacitor must be refreshed in order to preserve in the data value. Thus, when a sense operation charges a bit line, the associated storage capacitor will also be charged, refreshing the data value stored within.
Referring now to FIG. 1, a prior art sensing arrangement is set forth in block schematic diagram. The sensing arrangement is designated by the general reference character 100, and illustrates a portion of a RAM having "folded" bit lines. In such an arrangement, the bit lines are grouped into bit line pairs 102. The sensing arrangement of FIG. 1 includes n+1 bit line pairs, labeled as BL0/BL0.sub.-- to BLn-BLn.sub.--. Each bit line pair (BL0/BL0.sub.-- to BLn/BLn.sub.--) is coupled to an associated sense amplifier 104. The sense amplifiers are shown as SA0-SAn. Each of the sense amplifiers 104 is commonly coupled to a first power supply line 106 and a second power supply line 108. The first power supply line 106 is coupled to a high power supply voltage VCC by a p-channel metal-oxide-semiconductor (MOS) sense transistor P100. In a similar fashion, the second power supply line 108 is coupled to a low power supply voltage VSS by an n-channel MOS sense transistor N100. Transistor P100 is activated by a first sense amplifier enable signal, shown as Spc.sub.--. Transistor N100 is activated by a second sense amplifier enable signal, shown as Snc.
In a read operation, a row of memory cells is coupled to the bit line pairs 102, creating differential voltage signals thereon. The sense amplifiers 104 are then activated, by turning on transistors P100 and N100, supplying the power supply voltages VCC and VSS to the first and second power supply lines (106 and 108), respectively. The activation of the transistors P100 and N100 results in a current pulse, which propagates along the first power supply line 106, starting at the drain of transistor P100, and ending at sense amplifier SA0. The sense amplifiers 104 will not be able to charge a bit line in their respective pairs 102 until the current pulse is received. In this manner, the speed at which a power supply current is provided to a sense amplifier effects the speed of the overall memory device.
Referring now to FIG. 2, a second sense arrangement is set forth in a block schematic diagram. The second arrangement is designated by the general reference character 200, and is shown to include many of the same structures as the first sense arrangement 100, set forth in FIG. 1. The second arrangement 200 includes a number of bit line pairs 202, shown as BL0/BL0.sub.-- to BLn/BLn.sub.--, each coupled to a sense amplifier 204. The sense amplifiers 204 are labeled SA0-SAn. Unlike the first arrangement 100, in the second arrangement 200, each sense amplifier 204 has an associated p-channel and n-channel MOS sense transistor. The p-channel sense transistors are shown as P200-0 to P200-n, and correspond to sense amplifiers SA0-SAn, respectively. The n-channel sense transistors are shown as N200-0 to N200-n, and are connected to sense amplifiers SA0-SAn, respectively.
The second sense arrangement 200 operates in a similar fashion to the first arrangement. Memory cells place data on the bit line pairs 202, and the sense amplifiers 204 are activated to sense the data signals. Sense amplifier activation occurs by the Spc.sub.-- signal going low and the Snc signal going high. The high power supply voltage VCC is coupled to the sense amplifiers 204 by way of transistors P200-0 to P200-n, and the low power supply voltage VSS is coupled to the sense amplifiers 204 by way of transistors N200-0 to N200-n. The second arrangement 200 can provide for faster sensing speeds, as the speed of the sense operation depends upon the propagation of the Spc.sub.-- and Snc signals along the gates of transistors P200-0 to P200-n and N200-0 to N200-n. The speed of the Spc.sub.-- and Snc signals is faster than the propagation of current pulse along the first power supply line 106 in the arrangement of FIG. 1. Speed is also increased as each of the transistors P200-0 to P200-n can be sized to provide more current to their respective sense amplifiers 204, than in the case of the first arrangement 100. A drawback to the second arrangement 200 is that the peak current drawn by the sense amplifiers 204 may be considerable.
FIG. 3 illustrates a prior art sense amplifier that may be used as the sense amplifiers 104 in FIG. 1, or sense amplifiers 204 in FIG. 2. The sense amplifier is designated by the general reference character 300, and is shown to include a first complementary pair of p-channel and n-channel transistors (P300 and N300) which have their source-drain paths arranged in series. The sense amplifier 300 includes a second pair of complementary transistors P302 and N302, having their source drain paths arranged in series. The complementary pairs P300/N300 and P302/N302 are cross-coupled, with the gates transistors P300 and N300 being coupled to the common drains of the transistors P302/N302 and vice versa. The common drains of transistors P300/N300 form a first sense node 302. The common drains of transistors P302/N302 form an opposing second sense node 304. The first and second sense nodes (302 and 304) are coupled between a bit line pair 306. The bit lines of the bit line pair 306 are shown as BLn and BLn.sub.--. The sources of transistors P300 and P302 are commonly connected to first power supply node 308, and the sources of transistors N300 and N302 are commonly coupled to a second power supply node 310.
The sense amplifier 300 is activated by applying a high power supply voltage to the first supply node 308, and a low power supply voltage to the second power supply node 310. When activated, the sense amplifier 300 will drive its sense nodes (302 and 304) to opposite potentials according to the differential voltage on the bit line pair 306. For example, in the event the differential voltage results in bit line BLn being higher in potential than bit line BLn.sub.--, when the sense amplifier 300 is activated, transistor P300 will pull the first sense node 302 to the high power supply voltage, and transistor N302 will pull the second sense node 304 to the low power supply voltage.
It would be desirable to provide a sensing scheme for RAMs and/or ROMs that provides for rapid sensing of data signals, but does not suffer from the drawbacks of the prior art.